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DATA BULLETIN
MX828
Features
* * * * * * * * Fast CTCSS Detection Full Duplex CTCSS and SelCall Full 23/24 Bit DCS Codec SelCall Codec Non Predictive Tone Detection Low Power 3.3V/5.0V Operation Variable Gain Audio Filter Programmable: Tone Decoder Tone Encoder Modulator Drivers Comparator for RSSI * Pin compatible with reduced function MX818 * Full control via 4-Wire Serial Interface
CTCSS/DCS/SelCall Processor
PRELIMINARY INFORMATION Applications
* Radio Systems Requiring Sub-Audible Signaling Trunking Control Selective Calling Group Calling * Increased Efficiency Scanning Systems Trunking Systems
CTCSS
RADIO
Tx MOD1
FAST CTCSS SELCALL DCS CARRIER DETECT
MODULATOR RF DISCRIMINATOR
Tx MOD2
RSSI
ANALOG Rx
TIMER LEVEL CONTROL
AUDIO MSK DTMF LEVEL & VOLUME CONTROLS
(OPTIONAL)
AUDIO SIGNALS
AUDIO FILTER
MX828
KEYBOARD
HOST C
SERIAL C-BUS: DATA & CONTROL DISPLAY
MX829
The MX828 is a low power SelCall, CTCSS, and DCS signal processor designed for use in the latest generation of LMR (Land Mobile Radio) equipment where sub-audible signaling is required for functions such as Trunking Control, Selective Calling, and Group Calling applications. The MX828 is full duplex and offers many advanced features to assist in the design of new Sub-Audible and in-band based systems. These include: a programmable tone decoder which may be set to respond to between 1 and 15 CTCSS or SelCall tones with minimum software intervention, a Fast/Predictive CTCSS detector that can respond to a single programmed tone in less than 60ms or provide an output if CTCSS tone is present at the detector input, two high resolution tone encoders that accurately generate CTCSS or SelCall tones, and a full 23/24 bit DCS encoder and decoder. The MX828 also provides a general purpose timer, a comparator with a programmable threshold, and a summing amplifier with two adjustable gain blocks to facilitate design integration and reduce part count. The MX828 may be used with a 3.0 to 5.5 volt supply and is available in the following packages: 24-pin SSOP (MX828DS), 24-pin SOIC (MX828DW), and 24-pin PDIP (MX828P).
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
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MX828 PRELIMINARY INFORMATION
CONTENTS
Section Page
1. Block Diagram .................................................................................................................................. 3 2. Signal List ......................................................................................................................................... 4 3. External Components ...................................................................................................................... 5 4. General Description ......................................................................................................................... 6
4.1 Software Description ................................................................................................................................. 7 4.2 8-bit Write Only Registers ........................................................................................................................ 8 4.3 16-bit Write Only Registers ...................................................................................................................... 9 4.4 Write Only Register Description ............................................................................................................... 10 4.5 8-bit Read Only Registers ....................................................................................................................... 16 4.6 Read Only Register Description............................................................................................................... 16
5. Application Notes............................................................................................................................ 20
5.1 General .................................................................................................................................................... 20 5.2 Transmitters ............................................................................................................................................. 20 5.3 Receiver (CTCSS/SelCall Decoder) ........................................................................................................ 21 5.4 Receiver (CTCSS Fast/Predictive Detector) ............................................................................................ 21 5.5 Receiver (DCS Decoder) ......................................................................................................................... 21 5.6 General Purpose Timer (GPT) ................................................................................................................. 21 5.7 Full Duplex Modes ................................................................................................................................... 21
6. Performance Specification............................................................................................................. 26
6.1 Electrical Performance ............................................................................................................................. 26 6.2 Timing Diagrams ...................................................................................................................................... 31 6.3 Packaging ................................................................................................................................................ 32
MX*COM, Inc. reserves the right to change specifications at any time and without notice.
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
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MX828 PRELIMINARY INFORMATION
1. Block Diagram
R7 R6 C3 R2
TX AUDIO OUT CTCSS TX TONE GENERATOR SELCALL TX TONE GENERATOR DCS CODE GENERATOR
TX TONE
TX SUB AUDIO OUT
RX AUDIO OUT
SUM IN
SUM OUT
MOD 1 IN MOD 1
SUMMING AMP + MOD 1 ENABLE TRIM
CTCSS / DCS / SELCALL TX
VSS
C4 C6
23 / 24 bits
VBIAS
MOD 2
VBIAS VDD
GENERAL PURPOSE TIMER
TRIM MOD 2 ENABLE COMMAND DATA C - BUS INTERFACE AND CONTROL LOGIC REPLY DATA CS IRQ SERIAL CLOCK
R5
VDD
AUDIO BPF
AUDIO RX
6dB ATTENUATOR
R3
RX AMP OUT
CTCSS / DCS / SELCALL RX
ADC
C5 R4 Input from Demodulator C7
RX AMP IN
+
SUB AUDIO LPF DCS EQUALIZER FILTER
COMPARATOR 3-bit DAC
ADC
CTCSS/SELCALL TONE DECODER
VBIAS
RX AMP
ADC
DCS DECODER
CTCSS FAST TONE DETECTOR
XTAL/CLOCK
C1 C2 X1 R1
XTAL
COMPIN
Figure 1: Block Diagram
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
+
CBUS
-
CLOCK OSCILLATOR AND DIVIDERS
TX TONE A/D CAP2
C9
CTCSS PREDICTIVE TONE DETECTOR
COMPOUT
A/D CAP1
C8
CTCSS/DCS/SelCall Processor
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MX828 PRELIMINARY INFORMATION
2. Signal List
Pin No. 1 2 3 4 Name XTAL XTAL/CLOCK SERIAL CLOCK COMMAND DATA Type output input input input Description The inverted output of the on-chip oscillator. The input to the on-chip oscillator, for external Xtal circuit or clock. The "C-BUS" serial clock input. This clock, produced by the C, is used for timing transfer of commands and data to and from the device. (Figure 4). The "C-BUS" serial data input from the C. Data is loaded into this device in 8-bit bytes, MSB (B7) first, and LSB (B0) last, synchronized to the SERIAL CLOCK. (Figure 4). The "C-BUS" serial data output to the C. The transmission of REPLY DATA bytes is synchronized to the SERIAL CLOCK under the control of the CS input. This 3-state output is held at high impedance when not sending data to the C. (Figure 4). The "C-BUS" data loading control function: this input is provided by the C. Data transfer sequences are initiated, completed or aborted by the CS signal (Figure 4). This output indicates an interrupt condition to the C by going to a logic "0". This is a "wire-ORable" output, enabling the connection of up to 8 peripherals to 1 interrupt port on the C. This pin has a low impedance pulldown to logic "0" when active and a high-impedance when inactive. An external pullup resistor is required. The conditions that cause interrupts are indicated in the IRQ FLAG register and are effective if not masked out by a corresponding bit in the IRQ MASK register. The output of the comparator. The input to the comparator. An internal reference voltage for the CTCSS A/D. Bypassed to VSS with an external capacitor. An internal reference voltage for the DCS A/D. Bypassed to VSS with an external capacitor. Negative supply (ground). A bias line for the internal circuitry, held at VDD/2. This pin must be bypassed by a capacitor mounted close to the device pins. The inverting input to the Rx input amplifier. Output of the Rx input amplifier Output of the Rx audio filter section. Output of the SelCall tone generator. Input to the audio summing amplifier. Output of the audio summing amplifier. Input to MOD1 audio gain control. Output of the CTCSS or DCS Tx tone generator. Output of MOD1 audio gain control. Output of MOD2 audio gain control. Positive supply. Levels and voltages are dependent upon this supply. This pin should be bypassed to VSS by a capacitor. Table 1: Signal List
5
REPLY DATA
output
6
CS
input
7
IRQ
output
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
COMPOUT COMPIN A/D CAP 1 A/D CAP 2 VSS VBIAS RX AMP IN RX AMP OUT RX AUDIO OUT TX AUDIO OUT SUM IN SUM OUT MOD1 IN TX SUB AUDIO OUT MOD1 MOD2 VDD
output input output output Power output input output output output input output input output output output Power
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
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MX828 PRELIMINARY INFORMATION
3. External Components
XTAL X1 R1 XTAL/CLOCK C1 C2 VDD VDD XTAL XTAL/CLOCK SERIAL CLOCK COMMAND DATA REPLY DATA CS IRQ COMPOUT COMPIN A/D CAP1 A/D CAP2 VSS C8 C9
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
C6 VDD MOD2 MOD1 TX SUB AUDIO OUT MOD1 IN SUM OUT SUM IN TX AUDIO OUT
RX AUDIO OUT RX AMP OUT RX AMP IN VBIAS
VSS
R5 "C-BUS" INTERFACE
MX828
R6 C3 R2 R7 R3 C5
C4
R4 C7 Input from Demodulator
Figure 2: Recommended External Components
R1 R2 R3 R4 R5 R6 R7 C1 C2 Note 2
1M: 100k: 100k: 22k: Note 1 Note 1 22pF 22pF
5% 10% 10% 10% 10% 10% 10% 20% 20%
C3 C4 C5 C6 C7 C8 C9 X1 Note 3 Note 2
100pF 0.1F 100pF 0.1F 0.1F 1.0F to 3.3F 4.032MHz
20% 20% 20% 20% 20% 20% 20% 100ppm
Table 2: External Components
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
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MX828 PRELIMINARY INFORMATION
External Components Notes:
1.
R2, R6, R7 and C3 form the gain components for the Summing Amplifier. R6 and R7 should be chosen as required from the system specification, using the following formula: Tx Sub Audio Gain = -
R2 R6
Tx Audio Gain = -
R2 R7
2. R3, R4, C5 and C7 form the gain components for the Rx Input Amplifier. R4 should be chosen as required by the signal level, using the following formula: Gain = -
R3 R4
C7 x R4 should be chosen so as not to compromise the low frequency performance of this product. 3. For best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of VDD, peak to peak. Tuning fork crystals generally cannot meet this requirement. To obtain crystal oscillator design assistance, consult your crystal manufacturer.
4. General Description
The MX828 is a signaling encoder/decoder for use in land mobile radio equipment, see Figure 1. The transmitter section of the MX828 has independently controllable tone generators for sub-audio (CTCSS) and inband (SelCall) signaling. Also featured is a DCS code generator, which may be used in place of the CTCSS tone generator. The receiver section of the MX828 has a fast/predictive CTCSS tone detector which operates in parallel with a DCS decoder and a CTCSS/SelCall tone decoder. The latter is switchable to perform either CTCSS or SelCall tone decoding of a user-programmable set of up to 15 tones. In the CTCSS mode it performs a more accurate (but slower) analysis of the tones detected by the fast/predictive CTCSS tone detector, which is a single detector that is switchable to provide either a fast response to any CTCSS tone (FAST DETECT mode) or a fast response to a single user-programmed CTCSS tone (PREDICTIVE mode). Both the DCS transmit and receive bit rates are fixed at 134.4bps. Other functions on the MX828 are a comparator with programmable threshold level, a general purpose timer and a summing amplifier with two adjustable gain blocks, which may be used for two point modulation, for example. All MX828 functions are controlled by an external C over the "C-BUS" interface, a serial interface designed to reduce interference levels in radio equipment.
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
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MX828 PRELIMINARY INFORMATION
4.1 Software Description
4.1.1 Command Summary The following table contains a brief description of all valid Commands. Details follow below. DATA BYTE(S) REGISTER NAME General Reset Sub-Audio Control SelCall Sub-Audio Status Sub-Audio Set-Up CTCSS TX/ Fast RX Frequency RX Tone Program DCS Code DCS Code DCS Code General Control Audio Control General Purpose Timer SelCall TX SECTION 4.4.1 4.4.2 4.5 4.6.1 4.4.3 4.4.10 HEX ADDRESS COMMAND $01 $80 $81 $82 $83 READ / WRITE W W R W W BYTE 1 none Refer to Bit Description Refer to Bit Description Refer to Bit Description BYTE 2 none none none none
Specify Tx or Fast Rx Frequency per command $80 & $83 Bit descriptions 1 of 15 possible Registers Select & Decode Frequencies Byte 3 of 3 Byte 2 of 3 Byte 1 of 3 Refer to Bit Description Mod 1 Attenuation Refer to Bit Description none none none none Mod 2 Attenuation none
4.4.11 4.4.4 4.4.5 4.4.6 4.4.7 4.4.12 4.4.8 4.4.13 4.4.2 4.4.3 4.4.9 4.5 4.6.2
$84 $85 $86 $87 $88 $8A $8B $8D
W W W W W W W W
Specify TX SelCall Frequencies Refer to Bit Description Refer to Bit Description none none
IRQ Mask IRQ Flag
$8E $8F
W R
Table 3: Command Summary
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
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MX828 PRELIMINARY INFORMATION
4.1.2 Address/Commands Instructions and data are transferred, via "C-BUS", in accordance with the timing information given in Figure 4. Instruction and data transactions to and from the MX828 consist of an Address/Command (A/C) byte followed by either: (i) (ii) a further instruction or data (1 or 2 bytes) or a status or Rx data reply (1 byte)
4.2 8-bit Write Only Registers
HEX ADDRESS/ COMMAND REGISTER NAME BIT 7 (D7) BIT 6 (D6) BIT 5 (D5) BIT 4 (D4) BIT 3 (D3) BIT 2 (D2) BIT 1 (D1) BIT 0 (D0)
$01
GENERAL RESET
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
SUBAUDIO $80 SIGNALLING CONTROL TX ENABLE
TONE DECODER ENABLE
FAST DETECT ENABLE 0 0 FAST CTCSS LSB MODE DETECT/ PREDICTIVE
SELCALL TX ENABLE 0
DCS RX ENABLE
TONE DECODER BANDWIDTH
$82 SIGNALLING SET-UP MSB BIT 3 BIT 2 BIT 1
TONE DECODER MODE
SUBAUDIO TX MODE
DCS 23/24
BIT 0
DCS BYTE 3
$85 DCS BYTE 3 OPTIONAL MSB BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16
DCS BYTE 2
$86 DCS BYTE 2 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
DCS BYTE 1
$87 DCS BYTE 1 BIT 7 BIT 6 BIT 5 BPF $88 GENERAL CONTROL GENERAL $8B PURPOSE TIMER MSB BIT 7 BIT 6 GP TIMER $8E IRQ MASK $9C 0 IRQ MASK BIT 5 COMP 0 to 1 IRQ MASK BIT 4 COMP 1 to 0 IRQ MASK BIT 3 TONE IRQ MASK BIT 2 CTCSS FAST IRQ MASK 0 BIT 1 BPF ENABLE BPF UN-MUTE 6dB PAD BIT 4 MSB DAC BIT 2 DAC BIT 1 BIT 3 BIT 2 LSB DAC BIT 0 GP TIMER ENABLE GP TIMER RE-CYCLE BIT 1 LSB BIT 0
GENERAL PURPOSE TIMER
LSB BIT 0 DCS IRQ MASK
Reserved for later use
Table 4: 8-bit Write Only Registers
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
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MX828 PRELIMINARY INFORMATION
4.3 16-bit Write Only Registers
HEX ADDRESS/ COMMAND REGISTER NAME BIT 7 (D7) BIT 6 (D6) BIT 5 (D5) BIT 4 (D4) BIT 3 (D3) BIT 2 (D2) BIT 1 (D1) BIT 0 (D0)
CTCSS TX/ $83 FAST RX FREQUENCY (1) CTCSS TX/ FAST RX FREQUENCY (2) RX TONE $84 PROGRAM (1) RX TONE PROGRAM (2) AUDIO $8A CONTROL (1) AUDIO CONTROL (2) 0 0 MOD 2 ENABLE MSB BIT 4 0 0 MOD 1 ENABLE MSB BIT 4 BIT 7 BIT 6 BIT 5 BIT 4 MSB BIT 3 BIT 2 BIT 1 BIT 7 BIT 6 BIT 5 BIT 4 CTCSS (TX) NOTONE 0 0 MSB BIT 12
CTCSS TX/FAST RX FREQUENCY
BIT 11
BIT 10
BIT 9
BIT 8
CTCSS TX/FAST RX FREQUENCY
LSB BIT 3 BIT 2 BIT 1 BIT 0
TONE ADDRESS
LSB BIT 0 MSB BIT 11
TONE FREQUENCY
BIT 10
BIT 9
BIT 8
TONE FREQUENCY
LSB BIT 3 BIT 2 BIT 1 BIT 0
MOD 1
LSB BIT 3 BIT 2 BIT 1 BIT 0
MOD 2
LSB BIT 3 BIT 2 BIT 1 BIT 0
SELCALL TX TONE
$8D SELCALL TX (1) SELCALL NOTONE 0 0 MSB BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
SELCALL TX TONE
SELCALL TX (2) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0
Table 5: 16-bit Write Only Registers
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
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MX828 PRELIMINARY INFORMATION
4.4 Write Only Register Description
4.4.1 GENERAL RESET (Hex address $01) The reset command has no data attached to it. It sets the device registers into the specific (all powersaved) states as listed below:
REGISTER NAME SIGNALING CONTROL SELCALL & SUB-AUDIO STATUS SIGNALING SET-UP CTCSS TX / FAST RX FREQUENCY CTCSS TX / FAST RX FREQUENCY RX TONE PROGRAM RX TONE PROGRAM DCS BYTE 3 DCS BYTE 2 DCS BYTE 1 GENERAL CONTROL AUDIO CONTROL AUDIO CONTROL GENERAL PURPOSE TIMER SELCALL TX SELCALL TX IRQ MASK IRQ FLAG X = undefined (1) (2) $8E $8F (1) (2) $8B $8D (1) (2) (1) (2) $85 $86 $87 $88 $8A $84 HEX ADDRESS $80 $81 $82 $83 BIT 7 (D7) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 6 (D6) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 5 (D5) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 4 (D4) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 3 (D3) 0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 2 (D2) 0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 1 (D1) 0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 0 D0) 0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 6: GENERAL RESET (Hex address $01)
4.4.2 SIGNALING CONTROL Register (Hex address $80) This register is used to control the functions of the device as described below: SUBAUDIO TX ENABLE (Bit 7) TONE DECODER ENABLE (Bit 6) CTCSS FAST DETECT ENABLE (Bit 5) SELCALL TX ENABLE (Bit 2) Bit 7 should be set to "1" to enable the CTCSS/DCS subaudio transmitter. The subaudio Tx type will depend on the state of the SUBAUDIO TX MODE (Bit 1 SIGNALING SET-UP Register $82). Bit 6 should be set to "1" to enable the CTCSS/SelCall tone decoder or the DCS decoder. Note: See Bit 0 for DCS decoder operation. Bits 7 and 6 should not both be set to "1" when Bit 0 is set to "1" because the DCS function is half-duplex only. When this bit is "1", the FAST CTCSS DETECT or FAST CTCSS PREDICTIVE mode is enabled, depending upon the setting of FAST CTCSS MODE (Bit 3 SIGNALING SET-UP Register, $82). When this bit is "0", both FAST CTCSS DETECT and FAST CTCSS PREDICTIVE tone detectors are disabled. When this bit is "1" the SelCall transmitter is enabled. When this bit is "0" the SelCall transmitter is disabled and powersaved.
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
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MX828 PRELIMINARY INFORMATION
DCS RX ENABLE (Bit 0)
When this bit is "1", the DCS decoder is enabled. When this bit is "0" the DCS decoder is disabled. The DCS decoder and the subaudio (CTCSS or DCS) transmitter should not be enabled at the same time. Reserved for future use. These bits should be set to "0". Table 7: SIGNALING CONTROL Register (Hex address $80)
(Bits 4, 3, and 1)
4.4.3 SIGNALING SET-UP Register (Hex address $82) This register is used to define the signaling parameters, as described below: TONE DECODER BANDWIDTH (Bits 7, 6, 5 and 4) FAST CTCSS MODE (Bit 3) These four bits set the bandwidth of the CTCSS/SelCall tone decoder according to the table below: When CTCSS FAST DETECT ENABLE (Bit 5 SIGNALING CONTROL Register, $80) is "1", this bit selects the FAST CTCSS DETECT or the FAST CTCSS PREDICTIVE mode, according to the table below: If the CTCSS FAST DETECT ENABLE bit is "0" then both modes are deselected. When this bit is "1" the CTCSS/SelCall tone decoder is set to detect inband (SelCall) tones. When this bit is "0" the tone decoder is set to detect subaudio (CTCSS) tones. When this bit is "1" the subaudio transmitter will be set to transmit DCS signals, if enabled. When this bit is "0" the subaudio transmitter will be set to transmit CTCSS signals, if enabled. When this bit is "1" the DCS transmitter and decoder are configured for a 23-bit code. When this bit is "0" they are configured for a 24-bit code. Table 8: SIGNALING SET-UP Register (Hex address $82)
TONE DECODER MODE (Bit 2) SUBAUDIO TX MODE (Bit 1) DCS 23/24 (Bit 0)
BANDWIDTH Bit 7 Recommended for CTCSS Recommended for CCIR 1 1 1 1 1 1 Recommended for ZVEI 1 1 Bit 6 0 0 0 0 1 1 1 1 Bit 5 0 0 1 1 0 0 1 1 Bit 4 0 1 0 1 0 1 0 1 Will Decode 1.1% 1.3% 1.6% 1.8% 2.0% 2.2% 2.5% 2.7% Will Not Decode 2.4% 2.7% 2.9% 3.2% 3.5% 3.7% 4.0% 4.2%
Table 9: TONE DECODER BANDWIDTH
DETECT/PREDICTIVE Bit 3 0 1
Function DETECT mode PREDICTIVE mode
Table 10: FAST CTCSS MODE
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
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MX828 PRELIMINARY INFORMATION
4.4.4 DCS BYTE 3 Register (Hex address $85) 4.4.5 DCS BYTE 2 Register (Hex address $86) 4.4.6 DCS BYTE 1 Register (Hex address $87) These three bytes set the code that is transmitted or received in the DCS mode. The LSB bit "0" of the DCS BYTE 1 is transmitted first and the last bit is the MSB bit 23 of DCS BYTE 3 in the 24-bit mode or bit 22 in the 23-bit mode. See Table 22 or refer to the latest version of ANSI/TIA/EIA - 603 specification and programming documentation for DCS standard 23-bit codes. 4.4.7 GENERAL CONTROL Register (Hex address $88) This register is used to control the functions of the device as described below: BPF ENABLE (Bit 7) BPF UN-MUTE (Bit 6) When this bit is "1" the audio band-pass filter is enabled. When this bit is "0" the audio band-pass filter is disabled (powersaved). When this bit is "1" the audio band-pass filter output is switched to the RX AUDIO OUT pin. When this bit is "0" the output of the filter is disconnected from RX AUDIO OUT, which is then in a high impedance state. This control, along with BPF ENABLE, allows the filter to power up and settle internally before switching the output on, to avoid clicks when coming out of powersave. When this bit is "1" a 6dB attenuator is inserted into the output of the audio band-pass filter. When this bit is "0" the output of the audio band-pass filter is not attenuated. These three bits set the level of the digital to analogue converter that feeds the negative input of the comparator. The DAC can be set to one of eight levels equally spaced between VSS and VBIAS, not including VSS, but including VBIAS, i.e. with a 5V supply, the lowest level would be 312.5mV set by "000" in bits 2, 3 and 4 and the highest level would be 2.5V set by "111" in bits 2, 3 and 4. When this bit goes to a "1" the general purpose timer is restarted and its internal register is re-loaded from the value specified in the GENERAL PURPOSE TIMER Register (Hex address $8B). It will then count down from the count held in its internal register. When this bit is "0" the count down is disabled and the last pre-programmed value is retained in the timer's internal register. When this bit is "1" the general purpose timer will re-load its internal register from the value specified in the GENERAL PURPOSE TIMER Register (Hex Address $8B) when the count in the internal register reaches zero (i.e. the timeout has expired). It then restarts the count down, so that the timer continuously cycles. When this bit is "0" the general purpose timer will stop when the count in the internal register reaches zero (i.e. the timeout has expired). The timer can only be restarted by reloading a value into the GENERAL PURPOSE TIMER Register (Hex address $8B). If this bit is switched from "1" to "0" while the timer is enabled then the timer will complete the present count before stopping. Table 11: GENERAL CONTROL Register (Hex address $88)
BPF 6dB PAD (Bit 5) DAC (Bits 4, 3 and 2)
TIMER ENABLE (Bit 1)
TIMER RE-CYCLE (Bit 0)
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
13
MX828 PRELIMINARY INFORMATION
4.4.8 GENERAL PURPOSE TIMER (GPT) Register (Hex address $8B) This register is used to preset the value of a countdown timer. Once a binary value has been loaded into this register, it will be automatically transferred to an internal register within the timer. This internal register is then decremented at each count interval (1ms) until it reaches zero. On reaching zero, the GPT IRQ FLAG in the IRQ FLAG Register (Hex address $8F) is set to "1". An interrupt is generated on the IRQ pin if the GPT IRQ MASK in the IRQ MASK Register (Hex address $8E) is "1" otherwise the GPT IRQ FLAG remains set to "1" and no interrupt is generated. When the internal register has reached a count of zero, the action of the timer depends on the setting of the TIMER RECYCLE bit in the GENERAL CONTROL Register (Hex address $88). If the TIMER RE-CYCLE bit is "1" then the timer will re-load the countdown value from the GENERAL PURPOSE TIMER Register and restart the countdown from this value. If the TIME RE-CYCLE bit is "0" then the timer will stop and no further action or timer interrupts will take place until the GENERAL PURPOSE TIMER Register is re-loaded. Loading the GENERAL PURPOSE TIMER with "0" will cause the timer circuitry to be disabled (i.e. powersaved). 4.4.9 IRQ MASK Register (Hex address $8E) This register is used to control the interrupts (IRQs) as described below: (Bits 7 and 1) GPT IRQ MASK (Bit 6) COMP 0 to 1 IRQ MASK (Bit 5) COMP 0 to 1 IRQ MASK (Bit 4) TONE IRQ MASK (Bit 3) CTCSS FAST IRQ MASK (Bit 2) DCS IRQ MASK (Bit 0) Reserved for future use. These should be set to "0". When this bit is set to "1" it enables an interrupt that occurs when GPT IRQ FLAG (Bit 6, IRQ FLAG Register, $8F) changes from "0" to "1". When this bit is "0" the interrupt is masked. When this bit is set to "1" it enables an interrupt that occurs when the comparator output goes from "0" to "1". When this bit is set to "0" the interrupt is masked. When this bit is set to "1" it enables an interrupt that occurs when the comparator output goes from "1" to "0". When this bit is set to "0" the interrupt is masked. When this bit is set to "1" it enables an interrupt that occurs when the TONE IRQ FLAG (Bit 3, IRQ FLAG Register, $8F) changes from "0" to "1". When this bit is "0" the interrupt is masked. When this bit is set to "1" it enables an interrupt that occurs when the CTCSS FAST IRQ FLAG (Bit 2, IRQ FLAG Register, $8F) changes from "0" to "1". When this bit is "0" the interrupt is masked. When this bit is set to "1" it enables an interrupt that occurs when the DCS DECODE/NO DECODE FLAG (Bit 7, SELCALL & SUB-AUDIO STATUS Register $81) changes state. When this bit is set to "0" the interrupt is masked. Table 12: IRQ MASK Register (Hex address $8E)
4.4.10 CTCSS TX/FAST RX FREQUENCY Register (Hex address $83) This is a 16-bit register. Byte (1) is sent first. When the CTCSS fast detector is enabled, the bits 0 to 12 define the receive frequency which the fast predictive detector is looking for according to the formula below: fXTAL (Hz) A= 16 x fTONE (Hz) where A is the binary number programmed into the 13 bits. When the CTCSS transmitter is enabled, the bits 0 to 12 control the frequency of the transmitted CTCSS tones according to the formula above. When the fast detector and the transmitter are both enabled, bits 0-12 define the receive frequency which the fast predictive detector is looking for and the frequency of the transmitted tone according to the formula above. (i.e. Tx Tone = predictive tone). When Bit 7 in byte (1) is set to "1" the tone output is set at VBIAS or NOTONE without regard to the number "A" programmed. When Bit 7 is "0" the programmed tone is set on the output. Programming the bits 0 to 12 to "0" puts the Tx into powersave and the output goes to VBIAS. Powersave is also achieved by disabling the SUBAUDIO Tx and the CTCSS FAST DETECT.
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
14
MX828 PRELIMINARY INFORMATION
4.4.11 RX TONE PROGRAM Register (Hex address $84) This is a 16-bit register. Byte (1) is sent first. The two bytes are used to program the center frequencies of up to 15 tones in either the audio or sub-audio band that will be decoded by the receiver. Each tone is identified by its address in bits 7, 6, 5 and 4 of byte (1). The remaining 12 bits contain the data representing the tone frequency according to the formula below. If a tone is not required the 12 bits should be set to zero. Byte 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5
Byte 2
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
<------------------------ N -----------------------> N is the binary representation of the following decimal number (n):
<----------------------- R ------------------------> R is the nearest 6-bit binary representation of (r), where:
SUBAUDIO (CTCSS)
n = INT (948982 x fTONE / fXTAL)
SUBAUDIO (CTCSS)
r = ((237245/fXTAL) - (n/(4 x fTONE))) x 8400
INBAND (SELCALL)
n = INT (83036 x fTONE / fXTAL)
INBAND (SELCALL)
r = ((20759/fXTAL) - (n/(4 x fTONE))) x 96000
Table 13: RX TONE PROGRAM Register (Hex address $84) Example: To program 100Hz when using the recommended 4.032MHz Xtal in SUBAUDIO (CTCSS) mode. n= = N= r = = INT (948982 x 100 / 4.032 x 10^6) INT (23.536) = 23 010111 (binary) ((237245 / 4.032 x 106) - (23 / (4 x 100))) x 8400 11.26 11 (rounding up if exactly halfway) 001011 (binary)
R= =
Thus the 12-bit code is 010111001011 The Hex address represented by bits 7, 6, 5 and 4 in byte (1) is used as the code to indicate which tone has been decoded. This code appears in bits 3, 2, 1 and 0 of the SELCALL and SUB-AUDIO STATUS Register (Hex address $81). The 15 programmed tones use Hex addresses $0 - $E.
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
15
MX828 PRELIMINARY INFORMATION
4.4.12 AUDIO CONTROL Register (Hex address $8A) This is a 16-bit register. Byte (1) is sent first. Bits 0 - 5 of the first byte in this register are used to set the attenuation of the Modulator 1 amplifier and bits 0 - 5 of the second byte in this register are used to set the attenuation of the Modulator 2 amplifier, according to Table 14. BYTE 1
5 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Mod. 1 Attenuation Disabled (VBIAS) >40dB 12.0dB 11.6dB 11.2dB 10.8dB 10.4dB 10.0dB 9.6dB 9.2dB 8.8dB 8.4dB 8.0dB 7.6dB 7.2dB 6.8dB 6.4dB 6.0dB 5.6dB 5.2dB 4.8dB 4.4dB 4.0dB 3.6dB 3.2dB 2.8dB 2.4dB 2.0dB 1.6dB 1.2dB 0.8dB 0.4dB 0dB 5 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
BYTE 2
0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Mod. 2 Attenuation Disabled (VBIAS) >40dB 6.0dB 5.8dB 5.6dB 5.4dB 5.2dB 5.0dB 4.8dB 4.6dB 4.4dB 4.2dB 4.0dB 3.8dB 3.6dB 3.4dB 3.2dB 3.0dB 2.8dB 2.6dB 2.4dB 2.2dB 2.0dB 1.8dB 1.6dB 1.4dB 1.2dB 1.0dB 0.8dB 0.6dB 0.4dB 0.2dB 0dB
X = don't care MOD1 ENABLE (Bit 5, first byte) MOD2 ENABLE (Bit 5, second byte) (Bits 7 and 6, first and second bytes) When this bit is "1" the MOD1 attenuator is enabled. When this bit is "0" the MOD1 attenuator is disabled (i.e. powersaved). When this bit is "1" the MOD2 attenuator and the SUMMING AMP are enabled. When this bit is "0" they are both disabled (i.e. powersaved). Reserved for future use. These should be set to "0". Table 14: AUDIO CONTROL Register (Hex address $8A)
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
16
MX828 PRELIMINARY INFORMATION
4.4.13 SELCALL TX Register (Hex address $8D) This is a 16-bit register. Byte (1) is sent first. When the SELCALL transmitter is enabled, bits 0 to 12 control the frequency of the transmitted SELCALL tones according to the formula below: A= fXTAL (Hz) 4 x fTONE (Hz)
where A is the binary number programmed into the 13 bits. When Bit 7 (in the first 8 bits) is set to "1" the tone output is set at VBIAS or NOTONE without regard to the number "A" programmed. When Bit 7 is "0" the programmed tone is set on the output. Programming bits 0 through 12 to "0" places the Tx into powersave and the output goes to VBIAS. Powersave is also achieved by disabling the SELCALL Tx.
4.5 8-bit Read Only Registers
HEX ADDRESS/ COMMAND REGISTER NAME BIT 7 (D7) BIT 6 (D6) BIT 5 (D5) BIT 4 (D4) BIT 3 (D3) BIT 2 (D2) BIT 1 (D1) BIT 0 (D0)
SELCALL & $81 SUB-AUDIO STATUS
DCS DECODE/ NO DECODE
CTCSS FAST TONE GP TIMER COMP 0 to 1 IRQ FLAG 0 TONE DECODE COMP 1 to 0 IRQ FLAG MSB BIT 3 TONE IRQ FLAG
RX TONE
LSB BIT 2 CTCSS FAST IRQ FLAG 0 BIT 1 BIT 0 DCS IRQ FLAG
$8F
IRQ FLAG
0
IRQ FLAG
Table 15: 8-bit Read Only Registers
4.6 Read Only Register Description
4.6.1 SELCALL and SUB-AUDIO STATUS Register (Hex address $81) This register is used to indicate the status of the device as described below: DCS DECODE/ NO DECODE (Bit 7) CTCSS FAST TONE (Bit 6) When the DCS decoder is enabled this bit is continuously updated with the result. A "1" indicates a successful decode (with 3 or less errors). A "0" indicates a failure to decode. When Bit 5 in the SIGNALING CONTROL Register and Bit 3 in the SIGNALING SET-UP Register are set to enable FAST CTCSS DETECT mode, this bit will be set to "1" if a periodic tone is detected. If no periodic tone is detected this bit will be "0". When bits 5 and 3 are set to enable FAST CTCSS PREDICTIVE mode, this bit will be set to "1" if a periodic tone that matches the frequency programmed in the CTCSS TX/FAST RX FREQUENCY Register is detected. If no match is found this bit will be "0". When Bit 5 in the SIGNALING CONTROL Register is set to "0" this bit will be "0". (Bit 5) Reserved for future use. This will be set to "0" but should be ignored by the user's software.
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
17
MX828 PRELIMINARY INFORMATION
TONE DECODE (Bit 4)
This bit indicates the status of the tone decoder. A "1" indicates a tone has been detected (TONE DECODE) and a "0" indicates the loss of the tone (NOTONE). TONE DECODE means that a tone has been decoded and its characteristics are defined by the bandwidth (See SIGNALING SET-UP Register bits 7, 6, 5 and 4) and the RX TONE number (See SELCALL and SUB-AUDIO STATUS Register bits 3, 2, 1 and 0). When Bit 6 in the SIGNALING CONTROL Register is set to "0" the TONE DECODE bit 4 will be set to "0". Identification of a valid tone which is not in the pre-programmed list of up to 15 tones will cause the decoder to move to the TONE DECODE state with the RX TONE address of "1111" in bits 3, 2, 1 and 0; indicating a valid, but unrecognized, tone. Loss of tone, will cause the NOTONE timer to be started. If loss of tone continues for the duration of the timeout period, then the decoder will move to NOTONE state and the identification of pre-programmed tones will start again. These four bits hold a Hex number from $0 to $F. Numbers $0 to $E represent the address of the tone decoded according to the tones programmed in the RX TONE PROGRAM Register, $84. The Hex number $F indicates the presence of any tone that is not described by DECODER BANDWIDTH (Bits 7, 6, 5 and 4, SIGNALING SET-UP Register, $82) and FREQUENCY (Bits 11 - 0, RX TONE PROGRAM Register, $84). Table 16: SELCALL and SUB-AUDIO STATUS Register (Hex address $81)
RX TONE (Bits 3, 2, 1 and 0)
4.6.2 IRQ FLAG Register (Hex address $8F) This register is used to indicate when the device requires attention as below: (Bits 7 and 1) GPT IRQ FLAG (Bit 6) COMP 0 to 1 IRQ FLAG (Bit 5) COMP 1 to 0 IRQ FLAG (Bit 4) TONE IRQ FLAG (Bit 3) CTCSS FAST IRQ FLAG (Bit 2) DCS IRQ FLAG (Bit 0) Reserved for future use. These will be set to "0" but should be ignored by user's software. When the general purpose timer has reached zero in its internal register, this bit will be set to "1" to indicate the timeout has expired. This bit is cleared to "0" by a read of the IRQ FLAG Register (Hex address $8F). When the comparator output goes from "0" to "1" (i.e. when the input voltage is above the DAC output voltage) this bit will be set to "1" and an interrupt generated (if bit 5 of the IRQ MASK Register $8E is set to "1"). This bit is set to "0" when the IRQ FLAG Register $8F is read. When the comparator output goes from "1" to "0" this bit will be set to "1" and an interrupt generated (if bit 4 of the IRQ MASK Register $8E is set to "1"). This bit is set to "0" when the IRQ FLAG Register $8F is read. When RX TONE DECODE (Bit 4, SELCALL and SUB-AUDIO STATUS Register, $81) changes state this bit will be set to "1". This bit is cleared to "0" by a read of the IRQ FLAG Register (Hex address $8F). When CTCSS FAST TONE (Bit 6, SELCALL and SUB-AUDIO STATUS Register, $81) changes state this bit will be set to "1". This bit is cleared to "0" by a read of the IRQ FLAG Register (Hex address $8F). When DCS DECODE/NO DECODE (Bit 7 SELCALL and SUB-AUDIO STATUS Register, $81) changes state this bit will be set to "1". This bit is cleared to "0" by a read of the IRQ FLAG Register (Hex address $8F). Table 17: IRQ FLAG Register (Hex address $8F)
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
18
MX828 PRELIMINARY INFORMATION
The flow chart shows the following modes of operation for the example below: 1. 2. 3. 4. Decode Decode and Fast Detect Decode & Fast Predictive Transmit, e.g. Tx = 100Hz ) ) e.g. Address 3 = 100Hz, bandwidth = 2.7%, interrupt enabled )
Note: $8X is the Hex address/command.
Power Up
Clear registers $01
Rx or Tx?
Tx
Rx Program 100Hz into address 3 $84 (1) = 00110101 $84 (2) = 11001011 Program Tx Tone Generator to 100Hz $83 (1) = 00001001 $83 (2) = 11011000
Decoder & Fast Predictive
Decoder or Decoder & Fast Predictive ?
Enable Tx $80 = 10000000
Program bandwidth + to _ 2.7% & Fast Predictive $82 = 11111000
Decoder
Program bandwidth _ to + 2.7% $82 = 11110000 Program Fast Rx Frequency to 100Hz $83(1) = 00001001 $83(2) = 11011000
Decoder & Fast Detect
Decoder or Decoder & Fast Detector ?
Decoder
Enable IRQ masks (optional) $8E = 00001100
Enable IRQ mask (optional) $8E = 00001000
Enable Decoder & Fast Detect/Predictive $80 = 01100000
Enable Decoder $80 = 01000000
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
19
MX828 PRELIMINARY INFORMATION
The flow chart shows the decoder, fast detect/fast predictive and transmitter enabled with the following example. 1. 2. 3. 4. Tx tone generator = 100Hz Decoder programmed with 100Hz in address 3 Bandwidth setting = 2.7% Interrupt enabled
Note: $8X is the Hex address/command.
Power Up
Clear registers $01
Program Tx/Fast Rx Frequency to 100Hz $83 (1) = 00001001 $83 (2) = 11011000
Program 100Hz into address 3 $84 (1) = 00110101 $84 (2) = 11001011
Fast Detect or Fast Predictive ? Fast Detect
Fast Predictive
Program bandwidth to 2.7% $82 = 11110000
Program bandwidth to 2.7% & Fast Predictive $82 = 11111000
Enable IRQ mask (optinal) $8E = 00001100
Enable decoder, Tx & Fast Detect/Predictive $80 = 11100000
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
20
MX828 PRELIMINARY INFORMATION
5. Application
5.1 General
The MX828 is intended for use in radio systems where signaling is required for functions such as trunking, control, selective calling or group calling. The CTCSS fast/predictive detector is useful for the detection of occupied channels indicating either the presence of any sub-audio tone, or range of tones, depending if it is set in fast detect or predictive mode. This will increase the efficiency of scanning and trunking systems, reducing the average time allocated to assessing each channel. The facility to decode any of up to 15 programmed tones allows the use of tones for various signaling functions such as masking a free channel or identifying sub groups within a user's groups. Adjustable decoder bandwidths permit certainty and signal to noise performance to be traded when congestion or range limits the system performance.
5.2 Transmitters
5.2.1 CTCSS The CTCSS transmitter is enabled with Bit 7 in the SIGNALING CONTROL Register ($80) and bit 1 in the SIGNALING SET UP Register ($82). The Tx frequency is set using Bit 0 to Bit 12 in the CTCSS TX/FAST RX FREQUENCY Register ($83) using the formula below: A= fXTAL (Hz) 16 x fTONE (Hz)
where A is the binary number programmed into the 13 bits. When Bit 7 (in the first 8 bits) is set to "1" the tone output is set at VBIAS or NOTONE without regard to the number "A" programmed. When Bit 7 is "0" the programmed tone is set on the output. Programming the bits 0 to 12 to "0" puts the Tx into powersave and the output goes to VBIAS. Powersave is also achieved by disabling the SUBAUDIO Tx and the CTCSS FAST DETECT (Bits 7 and 5 in the SIGNALING CONTROL Register $80). 5.2.2 The SelCall transmitter The SelCall transmitter is enabled with Bit 2 in the SIGNALING CONTROL Register ($80). The Tx frequency is set using Bit 0 to Bit 12 in the SELCALL TX Register ($8D) using the formula below: A= fXTAL (Hz) 4 x fTONE (Hz)
where A is the binary number programmed into the 13 bits. When Bit 7 (in the first 8 bits) is set to "1" the tone output is set at VBIAS or NOTONE without regard to the number "A" programmed. When Bit 7 is "0" the programmed tone is set on the output. Programming the bits 0 to 12 to "0" puts the SelCall Tx into powersave and the output goes to VBIAS. Powersave is also achieved by disabling the SELCALL TX ENABLE (Bit 2 in the SIGNALING CONTROL Register $80). 5.2.3 DCS Transmitter The DCS transmitter is enabled with Bit 7 in the SIGNALING CONTROL Register ($80) and bit 1 in the SIGNALING SET UP Register ($82). The Tx data is set in the DCS BYTE 3, DCS BYTE 2 and DCS BYTE 1 Registers ($85, $86 and $87). Note: The DCS transmitter produces an inverted output. When the signal is fed through the summing amp, in an inverted configuration, the correct polarity of the DCS signal will be restored (The MOD1 and MOD2 amplifier blocks do not invert).
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
21
MX828 PRELIMINARY INFORMATION
5.3 Receiver (CTCSS/SelCall Decoder)
The CTCSS/SelCall decoder should first be set up according to the desired characteristics. This entails setting the TONE DECODER MODE Bit 2 of the SIGNALING SET UP Register ($82), and setting the TONE decoder bandwidth in the SIGNALING SET-UP Register ($82), also programming the center frequencies of the desired tones in the RX TONE PROGRAM Register ($84). (It can hold up to 15 different tones). Any tone can be in any location. When the device is decoding, the tones are scanned in the sequence of their location, i.e. $0 first and $E last. Once a tone is detected the remaining tones are not checked. Therefore if two tones are close enough in frequency for their bandwidths to overlap then the one in the lowest location will be detected. The TONE IRQ MASK in the IRQ MASK Register ($8E) should also be set as required. The TONE DECODER ENABLE in the SIGNALING CONTROL Register ($80) should then be set to "1". While in the CTCSS/SelCall decoder mode the fast/predictive detector may be enabled (see below). (Bit 5 in the SIGNALING CONTROL Register $80). When the CTCSS/SelCall decoder detects a change in its present state an IRQ will be generated and Bit 3 of the IRQ FLAG Register ($8F) will indicate this. The change that occurred can be read from Bit 4 of the SELCALL and SUB-AUDIO STATUS Register ($81) and if a tone is indicated by this bit then the number of that tone can be read from Bits 3, 2, 1 and 0 of the same register.
5.4 Receiver (CTCSS Fast/Predictive Detector)
This is used for detecting, in the fastest possible time, that sub-audio tones are present on the Rx channel. Response time is optimized for speed at the expense of frequency resolution. It is enabled using Bit 5 of the SIGNALING CONTROL Register ($80). It has an IRQ which may be unmasked with Bit 2 of the IRQ MASK Register ($8E). The FAST CTCSS MODE DETECT/PREDICTIVE Bit 3 in the SIGNALING SET-UP Register ($82) allows for one of two alternatives in the FAST mode. In DETECT mode it will detect any periodic tone in the sub-audio band and when in PREDICTIVE mode it will detect specific tones determined by the frequency set in the CTCSS TX/FAST RX FREQUENCY Register ($83) and the fixed PREDICTIVE mode bandwidth. Successful detection is indicated by the CTCSS FAST IRQ FLAG Bit 2 in the IRQ FLAG Register ($8F), and the CTCSS FAST TONE Bit 6 in the SELCALL and SUB-AUDIO STATUS Register ($81).
5.5 Receiver (DCS Decoder)
The incoming signal is matched with the DCS code programmed into the DCS BYTE 1/2/3 Registers. When the DCS decoder is enabled, the DCS DECODE/NO DECODE FLAG in Bit 7 of the SELCALL and SUB-AUDIO STATUS Register ($81) will be set if the decode is successful (3 or fewer errors). A ''0" flag indicates a failure to decode. This flag is updated for every bit of the incoming signal. In order to detect the DCS turn-off code (134Hz) the CTCSS tone decoder should also be enabled and programmed with this value. Once detected, this will cause a CTCSS tone decoder interrupt, the receiver audio output should then be muted.
5.6 General Purpose Timer (GPT)
This may be used in conjunction with the CTCSS/SelCall decoder to form part of the decode algorithm or as a timer for any other purpose. It has an 8-bit value in the GENERAL PURPOSE TIMER Register ($8B) set in units of 1msec, an IRQ FLAG in Bit 6 of the IRQ FLAG Register ($8F) and an IRQ MASK in Bit 6 of the IRQ MASK Register ($8E).
5.7 Full Duplex Modes
Although the device is specified as half duplex, the only functions that must operate as such are: DCS Tx DCS Tx CTCSS decode or or or DCS Rx CTCSS Tx SELCALL decode
All other functions are totally independent and therefore a full duplex CTCSS or full duplex SELCALL along with many other combinations are possible.
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
22
MX828 PRELIMINARY INFORMATION
5.7.1 Tx / Fast Rx Tone Table : CTCSS The following table lists the commonly used CTCSS tones and the corresponding values for programming the transmitter frequency / fast predictive frequency register (Hex address $83). Freq. (Hz) 67.0 69.3 71.9 74.4 77.0 79.7 82.5 85.4 88.5 91.5 94.8 97.4 100.0 103.5 107.2 110.9 Byte 1 (hex) E E D D C C B B B A A A 9 9 9 8 Byte 2 (hex) B1 34 B1 3B C9 5A EF 87 1F C2 62 1B D8 83 2F E0 Freq. (Hz) 114.8 118.8 123.0 127.3 131.8 136.5 141.3 146.2 151.4 156.7 159.8 162.2 167.9 173.8 179.9 183.5 Byte 1 (hex) 8 8 8 7 7 7 6 6 6 6 6 6 5 5 5 5 Byte 2 (hex) 93 49 1 BC 78 36 F7 BC 80 48 29 12 DD AA 79 5D Freq. (Hz) 186.2 189.9 192.8 196.6 199.5 203.5 206.5 210.7 218.1 225.7 229.1 233.6 241.8 250.3 254.1 Byte 1 (hex) 5 5 5 5 4 4 4 4 4 4 4 4 4 3 3 Byte 2 (hex) 49 2F 1B 2 EF D6 C4 AC 83 5D 4C 37 12 EF E0
Table 18: Tx/Fast Rx Tone Table CTCSS
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
23
MX828 PRELIMINARY INFORMATION
5.7.2 Rx Tone Program Tables : CTCSS The following table lists the commonly used CTCSS tones together with the values for programming the "RX TONE PROGRAM" register (Hex address $84). Note: The values for byte 1 and 2 below apply to tone address 0 only. These values will vary depending on the location they are programmed into. Freq. (Hz) 67.0 69.3 71.9 74.4 77.0 79.7 82.5 85.4 88.5 91.5 94.8 97.4 100.0 103.5 107.2 110.9 Byte 1 (hex) 3 4 4 4 4 4 4 5 5 5 5 5 5 6 6 6 Byte 2 (hex) D8 9 1B 4E 83 94 CB 2 14 4C 87 94 CB 7 45 82 Freq. (Hz) 114.8 118.8 123.0 127.3 131.8 136.5 141.3 146.2 151.4 156.7 159.8 162.2 167.9 173.8 179.9 183.5 Byte 1 (hex) 6 6 7 7 7 8 8 8 8 9 9 9 9 A A A Byte 2 (hex) C0 D1 10 50 C0 2 44 86 C9 C 48 82 C6 B 84 C2 Freq. (Hz) 186.2 189.9 192.8 196.6 199.5 203.5 206.5 210.7 218.1 225.7 229.1 233.6 241.8 250.3 254.1 Byte 1 (hex) A B B B B B C C C D D D E E E Byte 2 (hex) C9 8 44 83 8A C9 6 46 C3 41 48 89 8 88 C7
Table 19: Rx Tone Program Tables : CTCSS
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
24
MX828 PRELIMINARY INFORMATION
5.7.3 Tx Tone Program Table : SelCall The following two tables list commonly used SelCall tonesets together with the values for programming the `SELCALL TX' register ($8D).
EEA Freq. (Hz) 1981 1124 1197 1275 1358 1446 1540 1640 1747 1860 1055 930 2247 991 2110 Byte 1 (hex) 01 03 03 03 02 02 02 02 02 02 03 04 01 03 01 Byte 2 (hex) FD 81 4A 17 E6 B9 8F 67 41 1E BB 3C C1 F9 DE Freq. (Hz) 1981 1124 1197 1275 1358 1446 1540 1640 1747 1860 2400 930 2247 991 2110 CCIR Byte 1 (hex) 01 03 03 03 02 02 02 02 02 02 01 04 01 03 01 Byte 2 (hex) FD 81 4A 17 E6 B9 8F 67 41 1E A4 3C C1 F9 DE Freq. (Hz) 2400 1060 1160 1270 1400 1530 1670 1830 2000 2200 2800 810 970 885 2600 ZVEI 1 Byte 1 (hex) 01 03 03 03 02 02 02 02 01 01 01 04 04 04 01 Byte 2 hex) A4 B7 65 1A D0 93 5C 27 F8 CA 68 DC 0F 73 84 Freq. (Hz) 2400 1060 1160 1270 1400 1530 1670 1830 2000 2200 885 810 740 680 970 ZVEI 2 Byte 1 (hex) 01 03 03 03 02 02 02 02 01 01 04 04 04 05 04 Byte 2 (hex) A4 B7 65 1A D0 93 5C 27 F8 CA 73 DC 0F CA 0F
Table 20: Tx Tone Program Table : SelCall
5.7.4 Rx Tone Program Table : SelCall The following two tables list commonly used SelCall tonesets together with the values for programming the `RX TONE PROGRAM' register ($84) in each Tone Address location as shown.
EEA Tone Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Freq. (Hz) 1981 1124 1197 1275 1358 1446 1540 1640 1747 1860 1055 930 2247 991 2110 Byte 1 (hex) A 15 26 36 46 57 67 78 88 99 A5 B4 CB D5 EA Byte 2 (hex) A C3 D 85 D1 4D CB 4B CD 84 51 C4 83 A C5 Freq. (Hz) 1981 1124 1197 1275 1358 1446 1540 1640 1747 1860 2400 930 2247 991 2110 CCIR Byte 1 (hex) A 15 26 36 46 57 67 78 88 99 AC B4 CB D5 EA Byte 2 (hex) A C3 D 85 D1 4D CB 4B CD 84 44 C4 83 A C5 Freq. (Hz) 2400 1060 1160 1270 1400 1530 1670 1830 2000 2200 2800 810 970 885 2600 ZVEI 1 Byte 1 (hex) C 15 25 36 47 57 68 79 8A 9B AE B4 C4 D4 ED Byte 2 (hex) 44 53 D2 83 E C8 86 49 42 43 46 14 D8 86 45 Freq (Hz) 2400 1060 1160 1270 1400 1530 1670 1830 2000 2200 885 810 740 680 970 ZVEI 2 Byte 1 (hex) C 15 25 36 47 57 68 79 8A 9B A4 B4 C3 D3 E4 Byte 2 (hex) 44 53 D2 83 E C8 86 49 42 43 86 14 C8 80 D8
Table 21: Rx Tone Program Table : SelCall
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
25
MX828 PRELIMINARY INFORMATION
5.7.5 DCS Code Table The following table gives a list of DCS codes together with the corresponding programmed into the DCS BYTE registers for a 23-bit DCS sequence.
DCS Code 023 025 026 031 032 043 047 051 054 065 071 072 073 074 114 115 116 125 131 132 134 143 152 155 156 162 165 172 174 205 223 226 243 244 245 251 261 263 265 271 306 311 DCS Byte 3 ($85) 76 6B 65 51 5F 5B 0F 7C 6F 5D 67 69 2E 74 35 72 7C 07 3D 33 2E 37 1E 44 4A 6B 31 05 18 6E 68 7B 45 1F 58 62 17 5E 43 79 0C 38 DCS Byte 2 ($86) 38 78 D8 F8 58 68 D8 A8 48 18 98 38 68 78 E8 B8 18 B8 38 98 D8 A8 C8 D8 78 C8 D8 F8 B8 98 E8 08 B8 A8 F8 78 78 88 C8 48 F8 D8 DCS Byte 1 ($87) 13 15 16 19 1A 23 27 29 2C 35 39 3A 3B 3C 4C 4D 4E 55 59 5A 5C 63 6A 6D 6E 72 75 7A 7C 85 93 96 A3 A4 A5 A9 B1 B3 B5 B9 C6 C9 DCS Code 315 331 343 346 351 364 365 371 411 412 413 423 431 432 445 464 465 466 503 506 516 532 546 565 606 612 624 627 631 632 654 662 664 703 712 723 731 732 734 743 754 DCS Byte 3 ($85) 6C 23 29 3A 0E 68 2F 15 77 79 3E 4B 6C 62 7B 27 60 6E 3C 2F 41 0E 19 0C 5D 67 0F 01 72 7C 4C 24 39 22 0B 39 1E 10 0D 14 20
values (in Hex) which should be
DCS Byte 2 ($86) 68 E8 78 98 B8 58 08 88 69 C9 99 99 59 F9 89 E9 B9 19 69 89 B9 39 E9 79 99 19 59 F9 89 29 39 79 39 B9 D9 89 49 E9 A9 D9 F9
DCS Byte 1 ($87) CD D9 E3 E6 E9 F4 F5 F9 09 0A 0B 13 19 1A 25 34 35 36 43 46 4E 5A 66 75 86 8A 94 97 99 9A AC B2 B4 C3 CA D3 D9 DA DC E3 EC
Table 22: DCS Code Table
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
26
MX828 PRELIMINARY INFORMATION
6. Performance Specification
6.1 Electrical Performance
6.1.1 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. General Supply (VDD - VSS) Voltage on any pin to VSS Current VDD VSS Any other pin DW / P Package Total Allowable Power Dissipation at TAMB = 25C Derating above 25C Storage Temperature Operating Temperature DS Package Total Allowable Power Dissipation at TAMB = 25C Derating above 25C Storage Temperature Operating Temperature -55 -40 550 9 125 85 mW mW/C C C -55 -40 800 13 125 85 mW mW/C C C -30 -30 -20 30 30 20 mA mA mA Min. -0.3 -0.3 Max. 7.0 VDD + 0.3 Units V V
6.1.2 Operating Limits Correct operation of the device outside these limits is not implied. Notes Supply (VDD - VSS) Operating Temperature Xtal Frequency Min. 3.0 -40 4.0315968 Max. 5.5 85 4.0324032 Units V C MHz
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
27
MX828 PRELIMINARY INFORMATION
6.1.3 Operating Characteristics For the following conditions unless otherwise specified: Xtal Frequency = 4.032MHz Audio Level 0dB ref. = 308 mVRMS at 1kHz VDD = 3.3V to 5.0V, TAMB= 25C, TOP = -40C to 85C Composite Signal = 308 mVRMS at 1kHz + 75mVRMS Noise + 31 mVRMS Sub-Audio Signal Noise Bandwidth = 5kHz Band Limited Gaussian Notes DC Parameters VDD = 3.3V IDD All Powersaved FAST DETECT Enabled Rx Operating DCS, FAST DETECT and CTCSS or SelCall Tx Operating DCS or SelCall or SUB AUDIO DCS and SelCall VDD = 5.0V IDD All Powersaved FAST DETECT Enabled Rx Operating DCS, FAST DETECT and CTCSS or SelCall Tx Operating DCS or SelCall or SUB AUDIO DCS and SelCall "C-BUS" Interface Input Logic "1" Input Logic "0" Input Leakage Current Input Capacitance Output Logic "1" Output Logic "0" "Off" State Leakage Current AC Parameters TONE Decoder Sensitivity CTCSS Response Time De-response Time Frequency Range SelCall Response Time De-response Time Frequency Range Good Signal Good Signal 625 14 22 3000 ms ms Hz Composite Signal Composite Signal 60 140 145 253 ms ms Hz Pure Tone 5 -26.0 dB IOH = 120A IOL = 360A VOUT = VDD 6 90% 10% 10 Logic "1" or "0" -1.0 70% 30% 1.0 7.5 VDD VDD A pF VDD VDD A 1, 2 1, 2 4.5 5.0 6.0 6.5 mA mA 1, 2 5.5 7.5 mA 1, 2 1, 2 1.0 3.0 1.5 4.5 mA mA 2 2 1.5 2.5 3.0 4.0 mA mA 2 3.0 4.5 mA 2 2 0.5 1.7 1.0 2.5 mA mA Min. Typ. Max. Units
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
28
MX828 PRELIMINARY INFORMATION
DCS Decoder Bit-Rate Sync Time Sensitivity CTCSS Detector - Fast Detect Sensitivity Response Time Frequency Range CTCSS Detector - Fast Predictive Sensitivity Response Time Frequency Range Decode Bandwidth CTCSS Encoder Frequency Range Tone Frequency Resolution Tone Amplitude Tolerance Total Harmonic Distortion SELCALL Encoder Frequency Range Tone Frequency Resolution Tone Amplitude Tolerance Total Harmonic Distortion DCS Encoder Bit Rate Amplitude Tolerance Amplitude Audio Band-Pass Filter Passband Passband Gain (at 1.0kHz) Passband Ripple Stopband Attenuation Residual Hum and Noise Alias Frequency Output Impedance TX AUDIO OUT, TX SUB AUDIO OUT and RX AUDIO OUT Enabled Disabled Rx Amp and Summing Amp Open Loop Gain Unity Gain Bandwidth Input Impedance Output Impedance at 100Hz Open Loop 10 6.0 input = 1mV at 100Hz 70.0 5.0 dB MHz M k 10 2.0 500 k: k: wrt gain at 1.0kHz 1 1 8 8 8 8 -2 33.0 -50.0 63 300 0 +0.5 -1.0 871 3000 1 9 -1.0 2.0 134.4 +1.0 1 9 208 -1.0 0 2.0 3000 0.2 +1.0 60.0 253 0.3 +1.0 Hz % dB % Hz % dB % bps dB mVP-P Hz dB dB dB dBp kHz Pure CTCSS Tone Composite Signal 5 7 60 40 -26.0 37.0 253 dB ms Hz Hz Pure CTCSS Tone Composite Signal 60 1 5 58 -26.0 56.0 253 2 116 edges mVP-P dB ms Hz
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
29
MX828 PRELIMINARY INFORMATION
Transmitter Modulator Drives: Mod.1 Attenuator Attenuation Cumulative Attenuation Error Output Impedance Input Impedance Mod.2 Attenuator Attenuation Cumulative Attenuation Error Output Impedance General Purpose Timer Timing Period Range Count Interval Xtal/Clock Input Pulse Width Input Impedance Gain D/A Range Step Size Step Accuracy Input Impedance Output Impedance COMPIN COMPOUT Table 23: Operating Characteristics Operating Characteristics Notes: 1. At VDD = 5.0V only. Signal levels or currents are proportional to VDD. 2. Not including any current drawn from the device by external circuitry. 3. Small signal impedance, at VDD = 5.0V and TAMB = 25C. 4. Timing for an external input to the XTAL/CLOCK pin. 5. With input gain components set as recommended in Figure 2. 6. IRQ pin. 7. From one tone to another tone. 8. See filter response (Figure 3). 9. Measured at MOD 1 or MOD 2 output. 10. SUBAUDIO, SELCALL and DCS. 1 1 1 -30 10 1 312.5 312.5 30 2500 mV mV mV M k ('High' or 'Low' (at 100Hz) input = 1mVRMS at 100Hz 4 40.0 10.0 20.0 ns M dB 1 1 255 ms ms at 0dB wrt attenuation at 0dB 3 -0.2 -0.6 600 0 0.2 0.6 dB dB at 100Hz at 0dB wrt attenuation at 0dB 3 -0.2 -1.0 600 15.0 0 0.2 1.0 dB dB k
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
30
MX828 PRELIMINARY INFORMATION
10 0 -10 Gain (dB) -20 -30 -40 -50
300Hz 250Hz
-60 10 100
1000 Frequency (Hz)
3kHz
10000
100000
Figure 3: Audio Band-Pass Filter Frequency Response
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
31
MX828 PRELIMINARY INFORMATION
6.2 Timing Diagrams
For the following conditions unless otherwise specified: Xtal Frequency = 4.032MHz, VDD = 3.3V to 5.0V, TAMB = -40C to +85C. Parameter tCSE tCSH tHIZ tCSOFF tNXT tCK Notes: 1. Depending on the command, 1 or 2 bytes of COMMAND DATA are transmitted to the peripheral MSB (Bit 7) first, LSB (Bit 0) last. REPLY DATA is read from the peripheral MSB (Bit 7) first, LSB (Bit 0) last. 2. Data is clocked into and out of the peripheral on the rising SERIAL CLOCK edge. 3. Loaded commands are acted upon at the end of each command. 4. To allow for differing C serial interface formats "C-BUS" compatible ICs are able to work with either polarity SERIAL CLOCK pulses. "CS-Enable to Clock-High" Last "Clock-High to CS-High" "CS-High to Reply Output 3-state" "CS-High" Time between transactions "Inter-Byte" Time "Clock-Cycle" time 2.0 4.0 2.0 Min. 2.0 4.0 2.0 Typ. Max. Units s s s s s s
tCSOFF
CS
tNXT
SERIAL CLOCK
tNXT
tNXT
tCSE
tCK
COMMAND DATA
7
MSB
6
5
4
3
2
1
0
LSB
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
ADDRESS/COMMAND BYTE REPLY DATA
FIRST DATA BYTE
LAST DATA BYTE
tHIZ
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
LSB MSB FIRST REPLY DATA BYTE
Logic level is not important
LAST REPLY DATA BYTE
Figure 4: "C-BUS" Timing
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
32
MX828 PRELIMINARY INFORMATION
6.3 Packaging
Package Tolerances
A Z B E W L T X Y CK H J P
DIM. A B C E H J K L P T W X Y Z MIN.
0.597 (15.16) 0.286 (7.26) 0.093 (2.36) 0.390 (9.90) 0.003 (0.08) 0.013 (0.33) 0.036 (0.91)
TYP.
MAX.
0.613 (15.57) 0.299 (7.59) 0.105 (2.67) 0.419 (10.64) 0.020 (0.51) 0.020 (0.51) 0.046 (1.17)
Alternative Pin Location Marking
PIN 1
0.050 (1.27) 0.016 (0.41) 0.050 (1.27) 0.009 (0.23) 45 0 5 5 10 7 0.0125 (0.32)
NOTE : All dimensions in inches (mm.) Angles are in degrees
Figure 5: 24-pin SOIC Mechanical Outline: Order as part no. MX828DW
A
Package Tolerances
Z B E L
DIM. A B C E H J L P T X Y Z MIN. TYP. MAX.
0.318 (8.07) 0.328 (8.33) 0.205 (5.20) 0.213 (5.39) 0.066 (1.67) 0.079 (2.00) 0.312 (7.90) 0.301 (7.65) 0.002 (0.05) 0.008 (0.21) 0.010 (0.25) 0.015 (0.38) 0.022 (0.55) 0.037 (0.95) 0.026 (0.65) 0.005 (0.13) 0.009 (0.22) 0 8 7 9 4 10
PIN 1 X Y H J P
T
C
NOTE : All dimensions in inches (mm.) Angles are in degrees
Figure 6: 24-pin SSOP Mechanical Outline: Order as part no. MX828DS
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
33
MX828 PRELIMINARY INFORMATION
A
Package Tolerances
DIM. A B C E E1 H J J1 K L P T Y MIN. TYP. MAX.
1.270 (32.26) 1.200 (30.48) 0.555 (14.04) 0.500 (12.70) 0.151 (3.84) 0.220 (5.59) 0.600 (15.24) 0.670 (17.02) 0.590 (14.99) 0.625 (15.88) 0.015 (0.38) 0.045 (1.14) 0.015 (0.38) 0.023 (0.58) 0.040 (1.02) 0.065 (1.65) 0.066 (1.67) 0.074 (1.88) 0.121 (3.07) 0.160 (4.05) 0.100 (2.54) 0.008 (0.20) 0.015 (0.38) 7 NOTE : All dimensions in inches (mm.) Angles are in degrees
B
E1
Y
E
PIN1
T
K H L J J1 P
C
Figure 7: Figure 5: 24-pin PDIP Mechanical Outline: Order as part no. MX828P
(c) 1997 MX*COM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480161.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc (USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA) Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits. These companies are all 100% owned operating companies of the CML Microsystems Plc Group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. CML Microcircuits Product Prefix Codes Until the latter part of 1996, the differentiator between products manufactured and sold from MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX respectively. These products use the same silicon etc. and today still carry the same prefixes. In the latter part of 1996, both companies adopted the common prefix: CMX. This notification is relevant product information to which it is attached. CML Microcircuits (USA) [formerly MX-COM, Inc.] Product Textual Marking On CML Microcircuits (USA) products, the `MX-COM' textual logo is being replaced by a `CML' textual logo.
Company contact information is as below:
CML Microcircuits (UK)Ltd
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (USA) Inc.
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon, Essex, CM9 6WG, England Tel: +44 (0)1621 875500 Fax: +44 (0)1621 875600 uk.sales@cmlmicro.com www.cmlmicro.com
4800 Bethania Station Road, Winston-Salem, NC 27105, USA Tel: +1 336 744 5050, 0800 638 5577 Fax: +1 336 744 5054 us.sales@cmlmicro.com www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/ 06 Mactech Industrial Building, Singapore 349307 Tel: +65 7450426 Fax: +65 7452917 sg.sales@cmlmicro.com www.cmlmicro.com
D/CML (D)/2 May 2002

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